CLUT configure register
APB_FIFO_MASK | 1’b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1’b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode. |
BLEND0_CLUT_MEM_RST | Write 1 then write 0 to this bit to reset BLEND0 CLUT. |
BLEND1_CLUT_MEM_RST | Write 1 then write 0 to this bit to reset BLEND1 CLUT. |
BLEND0_CLUT_MEM_RDADDR_RST | Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. |
BLEND1_CLUT_MEM_RDADDR_RST | Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. |
BLEND0_CLUT_MEM_FORCE_PD | 1: force power down BLEND CLUT memory. |
BLEND0_CLUT_MEM_FORCE_PU | 1: force power up BLEND CLUT memory. |
BLEND0_CLUT_MEM_CLK_ENA | 1: Force clock on for BLEND CLUT memory. |